The present invention relates to the field of integrated circuits, and, more particularly, to an input circuit with common mode compatibility with respect to its supply nodes.
In various applications relating to analog signal processing, the common mode of the input signal may vary from the positive to the negative supply voltage such as, for example, with standard low voltage differential signals (LVDS) having variable voltages from 0 to 2.4V. For these applications, the input stages of the interface circuits should be able to accept a signal with such variations without significantly degrading the performance of the amplifier.
A typical application in which the circuit of the invention may be used is illustrated in FIGS. 1A and 1B. In the illustrated example, a digital signal, transmitted on an optical fiber, is received by a first integrated circuit IC1 installed on a printed circuit board. After having been processed, the signal is sent from the first integrated circuit IC1 by a transmission block Transmit Tx through the pins and the connecting metal tracks PCB tracks to a second integrated circuit IC2. The integrated circuit IC2 is installed on the same board and receives the signal by way of an input circuit thereof which amplifies the received analog signal to make it available at an appropriate level to logic circuitry CMOS logic.
While transmission of signals through the conducting tracks of the printed circuit board is commonly done in a differential mode according to standard LVDS, the input stage of the integrated circuit IC2 that receives the signal processed by the interfacing circuit IC1 may be single ended, as shown in FIG. 1A, or may have a differential output, as shown in FIG. 1B. If the input interfacing circuit IC1 is single ended, the output signal will have a certain average value Vavg. If the output is differential, the output signal will be centered on a certain common mode voltage Vcm.
Other circuits are commonly connected in cascade to the input interfacing circuit IC1, the first of which may be an analog gain circuit G. The gain circuit G is followed by a digital buffer stage which, in practice, may even be represented by a single circuit (e.g., an inverter) having a certain threshold voltage for discriminating zeroes and ones.
It will be appreciated that, for a correct interpretation of the signals that are fed to the block G, it is important that the amplitude of the signal corresponding to a logic value 1 remains above the threshold of discrimination. Further, the amplitude of the signal corresponding to a zero logic value should also remain below the threshold of discrimination for both single ended and differential signals.
FIGS. 2A and 2B are diagrams of the signals output by the input interfacing circuit for the case of a single ended or a differential output circuit when the input signal is an analog signal corresponding to a, certain sequence of ones and zeroes. In practice, the output signal Vout (in the case of single ended output) or Vout+ minus Voutxe2x88x92 (in the case of differential output) will have a shape more or less rounded and with a voltage swing (i.e., the difference between the maximum and the minimum value) typically between 250-400 mV, as illustratively shown.
As also shown in the illustrated examples, in the case of a differential output there will be a certain common mode voltage Vcm, while in the case of single ended output there will be an average voltage Vavg, both corresponding to the average output voltage following a long sequence of alternated zeroes and ones (FIG. 2A). The switching threshold of the input stage G of the digital circuitry (FIGS. 1A and 1B) will be fixed to a value to correspond to the average value Vavg or to the common mode value Vcm. Therefore, a fundamental prerequisite of the input circuit is that the output signal be centered with respect to these values (Vavg or Vcm), as the threshold of discrimination of the input digital value is fixed as a function thereof.
In this way, the level of the output signal may be shifted with respect to the level of the input signal without loosing data because the output signal is kept centered independently from the succession of values of the input signal, as shown in the examples of FIG. 2B and at (a) in FIG. 3. If, because of the characteristics of the input circuit, the output signal is not kept centered with respect to its average value or its common mode value, as shown at (c) in FIG. 3, it may happen that a digital value 1 is erroneously read as a zero by the digital circuit connected in cascade to the input circuit (or vice-versa). This may happen because the signal may remain below (or above) the switching threshold if a sufficiently long sequence of zeroes (or ones) determines a shift of the working point of the output node. This shift is either toward ground in the case of a long sequence of zeroes, as shown at (c) in FIG. 3, or toward the supply voltage in the case of a long sequence of ones.
A known prior art design approach for the input circuit is illustrated in FIG. 4 which utilizes two operational amplifiers (op-amps), one of which has a common mode compatibility toward the supply voltage (Vdd) and the other toward ground (GND). The voltage outputs are both single ended and connected in common to provide for a single ended output of the entire circuit.
The design illustrated in FIG. 4 has certain drawbacks. First, the output is single ended and is obtained by short circuiting the outputs of the two distinct operational amplifiers, which may conflict with each other. This may slow down the system because the circuit has to work even when the two parts are in conflict. This happens because of an unbalanced common mode, either toward the supply voltage (Vdd) or toward ground (GND), which causes one of the two pairs of input transistors of the two distinct operational amplifiers to start turning off.
Furthermore, the output node Vout is a high impedance node having a high gain and, as a result, is relatively slow. The high impedance implies that in the presence of certain input sequences there is a likelihood of losing data in the case illustrated at (c) in FIG. 3. In fact, in an integrated circuit a high impedance output node has a parasitic series capacitance toward the substrate creating a pole at a low frequency. This practically integrates the output signal and centers it on a short-term average value, producing the result shown at (c) in FIG. 3.
Yet another drawback of the above-described prior art design is that two reference voltages are needed, namely VBP2 and VBN2. The generation of these voltages may require further silicon area for implementation.
It is therefore an object of the invention to provide an analog input circuit which provides full input common mode compatibility toward supplies rails and provides for a low impedance output, thus reducing the risk of losing data, and with a circuit configuration that is relatively simple and integrable in a reduced silicon area with respect to prior art circuits.
In accordance with the invention, an analog input circuit may include a pair of differential transconductance input stages having input nodes connected in parallel and which are fed the analog input signal. One of the differential transconductance stages may have common mode compatibility toward the supply node at the highest potential, and the other stage may have common mode compatibility toward the supply node at the lowest potential. Furthermore, differential output currents of the transconductance input stages may be summed differentially on first and second input nodes of a differential converter stage, which converts the differential current signals to an amplified differential voltage output signal.
The analog input circuit in accordance with the invention has a relatively low output impedance which provides high speed, as well as enhanced stability of the working point of the circuit.